The present invention relates to a semiconductor memory device and a process of manufacturing the same. More particularly, the invention relates to a semiconductor memory device having a redundancy circuit for replacing a defective regular memory cell with a spare memory cell, and a process of manufacturing such a memory device replacement.
With the recent developments in semiconductor process technology, semiconductor memory devices have high integration and many functions. At the same time, the yield becomes lower due to fine processing of semiconductor memory devices. To improve the yield and remedy defective memory cells, there are provided spare memory cells on the same semiconductor substrate where regular memory cells are formed, whereby a defected regular memory cell is replaced with a spare memory cell.
Data writing process in mask ROMs is performed at the manufacturing stage so that it is to impossible afterwards to change the data of a memory cell having a defect.
A semiconductor memory device made of mask ROMs having a redundancy circuit for the remedy of a memory cell with a defect by replacing it with a spare one, is proposed in Japanese Patent Application No. 63-204802 (1988) filed by the same assignee of the present invention.
According to this proposal, there is provided a redundancy circuit having spare memory cells capable of remedying a defective memory cell in a mask ROM by writing data even after it has been manufactured, and allowing data storage without the supply of power. As spare memory cells, fuses are used for data writing wherein they are blown or not by a turn-on or turn-off current of a MOS transistor.
This proposal, however, has been found unsatisfactory in that the potential of a write word line fluctuates due to noise from another write word line when a current flows in a transistor connected to the latter line in order to blow a fuse. Accordingly, there arises the problem that a fuse which should not be blown may be blown due to noise upon the blowing of another fuse. The success rate of programming will therefore drop. Such failure occurs within the chip so that it cannot be dealt with externally.